Digital IC Design - Lab 5 - EE421L

Email: wolak@unlv.nevada.edu

September 22, 2021

Lab Description

This lab will focus on the design, layout, and simulation of CMOS inverters of two distinct sizes

Pre-Laboratory Procedure

- All previous laboratory work was backed up using .zip files and my personal Google Drive

- All material in Tutorial 3 were covered in entirety before the start of the laboratory session

Laboratory Objectives

1.) Design a 12u/6u CMOS inverter schematic with corresponding layout and symbol

2.) Design a 48u/24u CMOS inverter schematic with corresponding layout and symbol

3.) Design a testing schematic to drive a 100fF, 1pF, 10pF, and 100pF capactior for each inverter, and comment on the results

4.) Perform the simulations above again using the Cadence UltraSim simulator 

Laboratory Procedure

1.) Lab 5 begins with the layout and design of a 12um/600nm PMOS device and 6um/600nm NMOS device used to form an inverter logic gate. Below you can see the design schematic, layout, and symbol view.

Figures 1-3: 12u/6u inverter schematic, layout and extracted views with LVS confirmation visible

Figure 4: 12u/6u inverter symbol

2.) The second portion will involve the layout and design of a 48um/600nm PMOS device and 24um/600nm NMOS device used to form an inverter logic gate. Note: this device was designed using fingers to save overall space of the layout and create a more efficiently produced design. This can be accomplished by manipulating the multiplier value in the design's parameters for each PMOS and NMOS device. Below you can see the design schematic, layout, and symbol view.

Figures 7-8: 48u/24u inverter layout with LVS confirmation visible, and associated symbol view

3.) The next step will be designing a test schematic to drive a capacitive load for each inverter in order to test operation and overall performance at varying capacitance. Each design will run on a 5v DC VDD supply voltage and use a pulsed input of 0-5V DC to test operation. Below you can see the designed testing schematic for each device using the symbols designed above.

Figures 9-10: testing schamtics for each inverter design showing the variable CAP which will be varied through parametric analysis

Each design was simulated using parametric analysis from 100fF to 100pF in 10pF steps to coner all values in one single simulation. This method produces a cleaner outcome with all values displayed on one graph. See the results below for each inverter.

Figures 11-12: simulation results for each inverter showing a varied capacitance through parametric analysis

4.) UltraSim Simulation

The final step involves performing the same simulations above in the Cadence UltraSim environment. This can be perfomed by navigating to the Setup -> Simulator/Directory/Host and selecting UltraSim. NOTE: model libraries for each PMOS and NOMS device needed to be added again.

Figure 13: 12u/6u inverter Cadence UltraSim simulation varying load capacitance from 100fF-100pF

Figure 14:  48u/24u inverter Cadence UltraSim simulation varying load capacitance from 100fF-100pF

Conclusion 

After reviewing each simulation's results it is clear that the larger 48u/24u inverter size performs far better overall as capacitance values increased. Each device performed similarily under a very low load of 100fF but as the load increased the switching time for the output was far faster for the larger inverter and this design would be of greater value if switching speed at a higher load was desired. In the domain of high speed logic design, the larger inverter would be the best performance choice, but also comes with trade offs of requiring more current and chip size to operate efficiently.

As with all previous labs, material, simulations, layouts ad results were backed up using .zip files and my personal Google Drive

Return to EE421 Labs

Return to EE421 Lab Fall 2021